Problem set #4: The last parameter to each instruction is the store location. Use this code for the following questions: load A, %r1 // loads A into register 1 load B, %r2 add %r1, %r2, %r3 //adds r1+r2 and stores in r3 noop noop add %r3, %r1, %r1 noop noop add %r1, %r1, %r1 noop noop store %r1, A add %r2, %r2, %r2 noop noop store %r2, B 1) Rewrite the assembly code above as code in a high level language of your choice. Assume A,B,C are simply integer variables. 2) Assuming the pipeline is not filled, how long (how many clock cycles) does the code take to run (without forwarding) in a typical RISC architecture with 5 pipeline stages? Also assume that the load and store operations finish execution in one clock cycle, just like any other instruction. 3) Can you remove some of the bubbles (pipeline stalls) required by the code above by rearranging the code? Give one such rearrangement. Remember not to alter the meaning of the program. 4) If operand forwarding is available, how many of the no-ops can be removed from the above code? 5) Convert the following C++ code into assembly. Assume that the variable a is in register 1 and the variable b is in register 2. while (a < b) { a++; } b++; 6) What are the values of -4(%rbp), -8(%rbp) and -12(%rbp) when the following completes execution: main: movl $2, -4(%rbp) movl $3, -12(%rbp) movl $2, -8(%rbp) .L3: movl -8(%rbp), %eax cmpl -12(%rbp), %eax jge .L2 movl -4(%rbp), %eax imull -4(%rbp), %eax movl %eax, -4(%rbp) addl $1, -8(%rbp) jmp .L3 .L2: movl -4(%rbp), %eax 7) Describe RISC vs CISC and give an argument for using each. 8) Describe two types of compiler optimizations. 9) If opcodes are 5 bits long, there are 16 registers and memory addresses are 32 bits long, how long is the program from above (exclude no-ops)? 10) Convert the program from above to use 2-operand instructions. How many bits is the resulting program?