Problem set #3:

The last parameter to each instruction is the store location.
Use this code for the following questions:

load A, %r1    // loads A into register 1   
load B, %r2     
add %r1, %r2, %r3 //adds r1+r2 and stores in r3 
add %r3, %r1, %r1 
add %r1, %r1, %r1
store %r1, A
add %r2, %r2, %r2
store %r2, B


1) Rewrite the assembly code above as C++/Java code. Assume A,B,C are
simply integer variables.

2) Assuming the pipeline is not filled, how long (how many clock
cycles) does the code take to run (without forwarding) in a
typical RISC architecture?  Also assume that the load and store
operations finish execution in one clock cycle, just like any other
instruction.

3) Can you remove some of the bubbles (pipeline stalls) required by
the code above by rearranging the code? Give one such
rearrangement. Remember not to alter the meaning of the program.

4) Assume the pipeline is not filled, how long does the code take to
run with operand forwarding in a typical RISC architecture?

5) Convert the following C++ code into assembly. Assume that the
variable a is in register 1 and the variable b is in register 2.

while (a < b) {
  a++;
}

b++;